1. Technical Field
The present invention generally relates to semiconductor packages. More particularly, the invention relates to a semiconductor package and fabrication method that uses direct copper bonding to enhance performance and provide electro-optic connectivity.
2. Discussion
In the highly competitive computer industry, the trend toward higher processing speeds and increased functionality is well documented. While this trend is desirable to the consumer, it presents significant challenges to circuit designers as well as manufacturers. A particular area of concern relates to the design of semiconductor packages.
In a typical computing environment, an integrated circuit (IC) such as a processor is encapsulated in a dielectric material to form a semiconductor die (or IC wafer). The IC wafer often has various IC contact pads that connect to the components of the IC by way of vertically extending vias and horizontally extending wires or traces. In order to electrically connect the closely spaced IC contact pads to the various traces of an adjacent printed wiring board (PWB) such as a motherboard, a number of techniques have been used. One approach is to connect an intermediate wafer such as a chip interposer or host wafer to the IC wafer in order to form a larger and more manageable semiconductor package. The intermediate wafer has one or more intermediate contact pads providing through-connection to the board side of the intermediate wafer. Metalized vias are typically used to provide the above described through-connection. One conventional approach to connecting the two wafers is to use an indirect connection approach such as controlled collapse chip connection (C4). If the intermediate wafer has a socketable interconnection mechanism such as pins or ball grid array (BGA) balls, the semiconductor package can be directly mated with a socket that is hardwired to the PWB. Otherwise, a socketable interface is disposed between the semiconductor package and the socket. As processing speeds continue to increase and computing devices continue to shrink in size, the effects of packaging designs on signal throughput have drawn more attention.
One of the more recent developments has been to capitalize upon the bandwidth advantages provided by transmitting signals in the optical domain. Specifically, it has been determined that the use of optics to transfer high speed clock signals as well as input/output (I/O) signals can significantly enhance performance. Conventional semiconductor packages that make use of optics often provide an IC wafer and an intermediate wafer that has an optical arrangement. The optical arrangement will typically include a waveguide and a coupler such as a Bragg grating. The waveguide and coupler therefore provide a mechanism for transporting optical signals between an optical source such as a laser or light emitting diode (LED) and the adjacent IC wafer. It is important to note, however, that processing of the signal often occurs in the electrical domain. This is particularly true in the case of computer processors widely used in the industry. In such cases, it is common to provide a photodetector on the IC wafer that is aligned with the optical coupler during the fabrication process.
While the above-described conventional approach has been satisfactory in some circumstances, certain difficulties remain. One particular difficulty relates to the placement of the optical detector on the IC wafer. Specifically, it has been determined that C4 bonding results in a “gap” between the wafers, and that the gap can lead to a number of problems from an optical standpoint. For example, aligning the optical arrangement with the photodetector requires a significant amount of precision in order to adequately couple the optical energy across the interface between the two wafers. Furthermore, the indirect bonding approach results in gaps on the order of 60 microns that can allow optical energy to escape regardless of how well the wafers are aligned. While the above-described optical losses could be avoided to some degree by placing the optical detector on the intermediate wafer, it has been determined that C4 bonding can also present problems from an electrical standpoint. For example, unwanted interconnect delay, resistance, capacitance, and loop inductance can all result from the C4 balls that are disposed between the IC contact pads and the intermediate contact pads. Thus, manufacturers and designers of conventional electro-optic semiconductor packages are faced with the difficult choice between the optical losses associated with IC wafer placement of the optical detector and the electrical losses associated with intermediate wafer placement of the optical detector.